ATxmega128A3

ATxmega128A3 特性

• High-performance, Low-power AVR 8/16-bit XMEGA Microcontroller
• Non-volatile Program and Data Memories
  – 64K - 256K Bytes of In-System Self-Programmable Flash
  – 4K - 8K Boot Code Section with Independent Lock Bits
  – 2K - 4K Bytes EEPROM
  – 4K - 16K Bytes Internal SRAM
  External Bus Interface for up to 16M bytes SRAM
  External Bus Interface for up to 128M Bytes SDRAM
• Peripheral Features
  – Four-channel DMA Controller with support for external requests
  – Eight-channel Event System
  – Seven 16-bit Timer/Counters
  Four Timer/Counters with 4 Output Compare or Input Capture channels
  Three Timer/Counters with 2 Output Compare or Input Capture channels
  High Resolution Extensions on all Timer/Counters
  Advanced Waveform Extension on one Timer/Counter
  – Seven USARTs
  IrDA Extension on 1 USART
  – AES and DES Crypto Engine
  – Two Two-wire Interfaces with dual address match(I2C and SMBus compatible)
  – Three SPI (Serial Peripheral Interfaces)
  – 16-bit Real Time Counter with Separate Oscillator
  – Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
  – One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
  – Four Analog Comparators with Window compare function
  – External Interrupts on all General Purpose I/O pins
  – Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
• Special Microcontroller Features
  – Power-on Reset and Programmable Brown-out Detection
  – Internal and External Clock Options with PLL
  – Programmable Multi-level Interrupt Controller
  – Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
  – Advanced Programming, Test and Debugging Interfaces
  JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
  PDI (Program and Debug Interface) for programming, test and debugging
• I/O and Packages
  – 50 Programmable I/O Lines
  – 64-lead TQFP
  – 64-pad MLF
• Operating Voltage
  – 1.6 – 3.6V
• Speed performance
  – 0 – 12 MHz @ 1.6 – 3.6V
  – 0 – 32 MHz @ 2.7 – 3.6V

ATxmega128A3 概述

The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR?enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million
Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conventional
single-accumulator or CISC based microcontrollers.
The XMEGA A3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose
I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare
modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Peripheral
Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional
differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
The XMEGA A3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consumption.
In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock for each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The program
Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download the application program to the Flash
memory. The Bootloader software in the Boot Flash section will continue to run while the Application
Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a powerful
microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
The XMEGA A3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.

ATxmega128A3 订购型号

ATxmega128A3 技术支持

1. ATMEL 爱特梅尔AVR 微控制器 ATxmega128A3 中文数据手册DataSheet 下载. PDF
2. ATMEL 爱特梅尔AVR 微控制器ATxmega128A3 数据手册DataSheet 下载. PDF
3. ATMEL 爱特梅尔半导体公司产品线. PDF (编号:Atmel Products)
4. Atmel 爱特梅尔AVR 微控制器简介.PDF (编号:Tech AVR 000)MLF32
5. 面向新手的AVR开发工具,及基本知识.PDF(编号:Tech AVR 001)
6. 使用AVR 定时/计数器的PWM功能设计要点 .PDF (编号:Tech AVR 002)